Did you know that the Intel Nehalem Xeon 55xx series CPU uses 40-bits for memory addressing, even though it’s a 64-bit CPU? This means it can address a maximum of half-a-terabyte of memory. Consider the table below and see that 40-bit can address up to 512GB – the (current) configuration of a UCS blade therefore needs to fit its memory into this size, and 384GB does that.
Gabrie had a point when he asked “So why doesn’t a UCS blade use the full 512GB?” This is purely down to combination of memory channels, sub-channels/slots and DIMMs with the Cisco Extended Memory Technology – here’s a great Cisco page on the whole shebang. Basically, the maximum configuration is:
To get more memory would mean increasing one or more of channels, slots, or DIMM sizes and none of these is a trivial change and would make the available memory > 40 bits addressable:
- To increase the number of CPU memory channels = CPU architecture change
- To increase the number of memory slots = decrease in memory speed which severe impact on performance
- To increase the size of DIMMs = significant $cost and pushes well over the 512GB addressable
Thanks to Gabrie for making me add this extra piece! You can get to Gabrie’s blog here: http://www.gabesvirtualworld.com/
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And before all the AMD fanboys jump in, Opterons also have an addressable physical memory limit of 40bits…
The Cisco Announcements have always said 576 GB with two sockets. Can someone explain why it is not 384×2 for two sockets?
Can you link to an announcement that states 576GB on a UCS blade? Thanks! Oh hang on, I found 3 – the register x 2, and you!